1. Technical Field
The present invention relates generally to data processing and, in particular, to servicing processor operations in a data processing system. Still more particularly, the present invention relates to a data processing system, processor and method of data processing in which selected processor memory access requests are serviced on a fixed schedule.
2. Description of the Related Art
A conventional symmetric multiprocessor (SMP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and which generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.
Cache memories are commonly utilized to temporarily buffer memory blocks that might be accessed by a processor in order to speed up processing by reducing access latency introduced by having to load needed data and instructions from memory. In some multiprocessor (MP) systems, the cache hierarchy includes at least two levels. The level one (L1), or upper-level cache is usually a private cache associated with a particular processor core and cannot be accessed by other cores in an MP system. Typically, in response to a memory access instruction such as a load or store instruction, the processor core first accesses the directory of the upper-level cache. If the requested memory block is not found in the upper-level cache, the processor core then access lower-level caches (e.g., level two (L2) or level three (L3) caches) for the requested memory block. The lowest level cache (e.g., L3) is often shared among several processor cores.
In a conventional lower level cache, processor memory access requests are serviced by a state machine dispatched from a pool of identical state machines. Because each of these state machines must handle both load and store accesses under both cache hit and cache miss scenarios, the state machines tend to be complex in design and large in physical area, meaning that die size limitations can impact the number of state machines that can be conveniently be implemented, and hence, the number of concurrent processor operations that can be serviced. In addition, the complexity of the state machine design adversely impacts cache access latencies.